-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "12/11/2021 22:13:03"

-- 
-- Device: Altera EP4CGX15BF14C6 Package FBGA169
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIV;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	cnt100 IS
    PORT (
	rst : IN std_logic;
	clk : IN std_logic;
	cntout1 : BUFFER std_logic_vector(3 DOWNTO 0);
	cntout2 : BUFFER std_logic_vector(3 DOWNTO 0)
	);
END cnt100;

-- Design Ports Information
-- cntout1[0]	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntout1[1]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntout1[2]	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntout1[3]	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntout2[0]	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntout2[1]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntout2[2]	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntout2[3]	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- rst	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF cnt100 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_cntout1 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_cntout2 : std_logic_vector(3 DOWNTO 0);
SIGNAL \rst~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \cntout1[0]~output_o\ : std_logic;
SIGNAL \cntout1[1]~output_o\ : std_logic;
SIGNAL \cntout1[2]~output_o\ : std_logic;
SIGNAL \cntout1[3]~output_o\ : std_logic;
SIGNAL \cntout2[0]~output_o\ : std_logic;
SIGNAL \cntout2[1]~output_o\ : std_logic;
SIGNAL \cntout2[2]~output_o\ : std_logic;
SIGNAL \cntout2[3]~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \cntout2~3_combout\ : std_logic;
SIGNAL \rst~input_o\ : std_logic;
SIGNAL \rst~inputclkctrl_outclk\ : std_logic;
SIGNAL \cntout2[3]~reg0_q\ : std_logic;
SIGNAL \cntout2~0_combout\ : std_logic;
SIGNAL \cntout2[0]~reg0_q\ : std_logic;
SIGNAL \cntout2[2]~2_combout\ : std_logic;
SIGNAL \cntout2[2]~reg0_q\ : std_logic;
SIGNAL \cntout2~1_combout\ : std_logic;
SIGNAL \cntout2[1]~reg0_q\ : std_logic;
SIGNAL \Equal0~0_combout\ : std_logic;
SIGNAL \cntout1[2]~2_combout\ : std_logic;
SIGNAL \cntout1[2]~reg0_q\ : std_logic;
SIGNAL \cntout1~1_combout\ : std_logic;
SIGNAL \cntout1[1]~reg0_q\ : std_logic;
SIGNAL \cntout1~3_combout\ : std_logic;
SIGNAL \cntout1[3]~reg0_q\ : std_logic;
SIGNAL \cntout1~0_combout\ : std_logic;
SIGNAL \cntout1[0]~reg0_q\ : std_logic;
SIGNAL \ALT_INV_rst~inputclkctrl_outclk\ : std_logic;

BEGIN

ww_rst <= rst;
ww_clk <= clk;
cntout1 <= ww_cntout1;
cntout2 <= ww_cntout2;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\rst~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \rst~input_o\);

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);
\ALT_INV_rst~inputclkctrl_outclk\ <= NOT \rst~inputclkctrl_outclk\;

-- Location: IOOBUF_X14_Y0_N2
\cntout1[0]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cntout1[0]~reg0_q\,
	devoe => ww_devoe,
	o => \cntout1[0]~output_o\);

-- Location: IOOBUF_X8_Y0_N2
\cntout1[1]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cntout1[1]~reg0_q\,
	devoe => ww_devoe,
	o => \cntout1[1]~output_o\);

-- Location: IOOBUF_X14_Y0_N9
\cntout1[2]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cntout1[2]~reg0_q\,
	devoe => ww_devoe,
	o => \cntout1[2]~output_o\);

-- Location: IOOBUF_X12_Y0_N9
\cntout1[3]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cntout1[3]~reg0_q\,
	devoe => ww_devoe,
	o => \cntout1[3]~output_o\);

-- Location: IOOBUF_X20_Y0_N2
\cntout2[0]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cntout2[0]~reg0_q\,
	devoe => ww_devoe,
	o => \cntout2[0]~output_o\);

-- Location: IOOBUF_X12_Y0_N2
\cntout2[1]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cntout2[1]~reg0_q\,
	devoe => ww_devoe,
	o => \cntout2[1]~output_o\);

-- Location: IOOBUF_X8_Y0_N9
\cntout2[2]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cntout2[2]~reg0_q\,
	devoe => ww_devoe,
	o => \cntout2[2]~output_o\);

-- Location: IOOBUF_X10_Y0_N9
\cntout2[3]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cntout2[3]~reg0_q\,
	devoe => ww_devoe,
	o => \cntout2[3]~output_o\);

-- Location: IOIBUF_X16_Y0_N15
\clk~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: CLKCTRL_G17
\clk~inputclkctrl\ : cycloneiv_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: LCCOMB_X14_Y1_N2
\cntout2~3\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cntout2~3_combout\ = (\cntout2[2]~reg0_q\ & (\cntout2[3]~reg0_q\ $ (((\cntout2[1]~reg0_q\ & \cntout2[0]~reg0_q\))))) # (!\cntout2[2]~reg0_q\ & (\cntout2[3]~reg0_q\ & ((\cntout2[0]~reg0_q\) # (!\cntout2[1]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100010110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntout2[2]~reg0_q\,
	datab => \cntout2[1]~reg0_q\,
	datac => \cntout2[3]~reg0_q\,
	datad => \cntout2[0]~reg0_q\,
	combout => \cntout2~3_combout\);

-- Location: IOIBUF_X16_Y0_N22
\rst~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_rst,
	o => \rst~input_o\);

-- Location: CLKCTRL_G19
\rst~inputclkctrl\ : cycloneiv_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \rst~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \rst~inputclkctrl_outclk\);

-- Location: FF_X14_Y1_N3
\cntout2[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cntout2~3_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cntout2[3]~reg0_q\);

-- Location: LCCOMB_X14_Y1_N4
\cntout2~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cntout2~0_combout\ = (!\cntout2[0]~reg0_q\ & ((\cntout2[2]~reg0_q\) # ((!\cntout2[1]~reg0_q\) # (!\cntout2[3]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntout2[2]~reg0_q\,
	datab => \cntout2[3]~reg0_q\,
	datac => \cntout2[0]~reg0_q\,
	datad => \cntout2[1]~reg0_q\,
	combout => \cntout2~0_combout\);

-- Location: FF_X14_Y1_N5
\cntout2[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cntout2~0_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cntout2[0]~reg0_q\);

-- Location: LCCOMB_X14_Y1_N28
\cntout2[2]~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cntout2[2]~2_combout\ = \cntout2[2]~reg0_q\ $ (((\cntout2[1]~reg0_q\ & \cntout2[0]~reg0_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \cntout2[1]~reg0_q\,
	datac => \cntout2[2]~reg0_q\,
	datad => \cntout2[0]~reg0_q\,
	combout => \cntout2[2]~2_combout\);

-- Location: FF_X14_Y1_N29
\cntout2[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cntout2[2]~2_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cntout2[2]~reg0_q\);

-- Location: LCCOMB_X14_Y1_N30
\cntout2~1\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cntout2~1_combout\ = (\cntout2[1]~reg0_q\ & (!\cntout2[0]~reg0_q\ & ((\cntout2[2]~reg0_q\) # (!\cntout2[3]~reg0_q\)))) # (!\cntout2[1]~reg0_q\ & (((\cntout2[0]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111110110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntout2[2]~reg0_q\,
	datab => \cntout2[3]~reg0_q\,
	datac => \cntout2[1]~reg0_q\,
	datad => \cntout2[0]~reg0_q\,
	combout => \cntout2~1_combout\);

-- Location: FF_X14_Y1_N31
\cntout2[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cntout2~1_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cntout2[1]~reg0_q\);

-- Location: LCCOMB_X14_Y1_N12
\Equal0~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \Equal0~0_combout\ = (\cntout2[1]~reg0_q\ & (\cntout2[3]~reg0_q\ & (!\cntout2[0]~reg0_q\ & !\cntout2[2]~reg0_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntout2[1]~reg0_q\,
	datab => \cntout2[3]~reg0_q\,
	datac => \cntout2[0]~reg0_q\,
	datad => \cntout2[2]~reg0_q\,
	combout => \Equal0~0_combout\);

-- Location: LCCOMB_X14_Y1_N8
\cntout1[2]~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cntout1[2]~2_combout\ = \cntout1[2]~reg0_q\ $ (((\cntout1[1]~reg0_q\ & (\cntout1[0]~reg0_q\ & \Equal0~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntout1[1]~reg0_q\,
	datab => \cntout1[0]~reg0_q\,
	datac => \cntout1[2]~reg0_q\,
	datad => \Equal0~0_combout\,
	combout => \cntout1[2]~2_combout\);

-- Location: FF_X14_Y1_N9
\cntout1[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cntout1[2]~2_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cntout1[2]~reg0_q\);

-- Location: LCCOMB_X14_Y1_N26
\cntout1~1\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cntout1~1_combout\ = (\cntout1[1]~reg0_q\ & (!\cntout1[0]~reg0_q\ & ((\cntout1[2]~reg0_q\) # (!\cntout1[3]~reg0_q\)))) # (!\cntout1[1]~reg0_q\ & (((\cntout1[0]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntout1[3]~reg0_q\,
	datab => \cntout1[2]~reg0_q\,
	datac => \cntout1[1]~reg0_q\,
	datad => \cntout1[0]~reg0_q\,
	combout => \cntout1~1_combout\);

-- Location: FF_X14_Y1_N27
\cntout1[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cntout1~1_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	ena => \Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cntout1[1]~reg0_q\);

-- Location: LCCOMB_X14_Y1_N22
\cntout1~3\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cntout1~3_combout\ = (\cntout1[1]~reg0_q\ & ((\cntout1[2]~reg0_q\ & (\cntout1[3]~reg0_q\ $ (\cntout1[0]~reg0_q\))) # (!\cntout1[2]~reg0_q\ & (\cntout1[3]~reg0_q\ & \cntout1[0]~reg0_q\)))) # (!\cntout1[1]~reg0_q\ & (((\cntout1[3]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntout1[1]~reg0_q\,
	datab => \cntout1[2]~reg0_q\,
	datac => \cntout1[3]~reg0_q\,
	datad => \cntout1[0]~reg0_q\,
	combout => \cntout1~3_combout\);

-- Location: FF_X14_Y1_N23
\cntout1[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cntout1~3_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	ena => \Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cntout1[3]~reg0_q\);

-- Location: LCCOMB_X14_Y1_N24
\cntout1~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cntout1~0_combout\ = (!\cntout1[0]~reg0_q\ & (((\cntout1[2]~reg0_q\) # (!\cntout1[1]~reg0_q\)) # (!\cntout1[3]~reg0_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntout1[3]~reg0_q\,
	datab => \cntout1[2]~reg0_q\,
	datac => \cntout1[0]~reg0_q\,
	datad => \cntout1[1]~reg0_q\,
	combout => \cntout1~0_combout\);

-- Location: FF_X14_Y1_N25
\cntout1[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cntout1~0_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	ena => \Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cntout1[0]~reg0_q\);

ww_cntout1(0) <= \cntout1[0]~output_o\;

ww_cntout1(1) <= \cntout1[1]~output_o\;

ww_cntout1(2) <= \cntout1[2]~output_o\;

ww_cntout1(3) <= \cntout1[3]~output_o\;

ww_cntout2(0) <= \cntout2[0]~output_o\;

ww_cntout2(1) <= \cntout2[1]~output_o\;

ww_cntout2(2) <= \cntout2[2]~output_o\;

ww_cntout2(3) <= \cntout2[3]~output_o\;
END structure;


